1. Field of the Invention
The present invention relates to correlation detectors, and more particularly to correlation detectors which utilize arithmetic sign control portions to economically operate.
2. Background Information
Correlation detectors (which are mathematically equivalent to, and in this disclosure will be considered as identical to, matched filters) are often used to detect sinusoidal signals under low signal-to-noise-ratio (hereafter referred to as "SNR") conditions. Such a prior art detection scheme is shown in FIG. 1 which is similar to that which is illustrated in page 340 of Detection, Estimation, and Modulation Theory, H. L. Van Trees, John Wiley and Sons, 1968. A noisy input signal is digitized by the analog-to-digital (hereafter referred to as "A/D") converter and into an output signal which is routed to an in-phase correlation portion and a quadrature correlation portion. Each correlation portion multiplies a noisy signal with the complex reference signal and integrates the result. (The complex reference signal is a cosine and sine wave at the signal's frequency). The two integrated products are then squared, summed together and compared to a threshold. If a threshold is exceeded, detection is indicated.
In practice, the above detection technique works quite well. However, high speed A/D converters are usually expensive, large and power hungry. Also, the correlation portions utilize digital multipliers which are power hungry when operated at high speeds, are relatively expensive and require significant processing time. The present invention relates to a technique that performs the above correlation/detection operation without the need for an A/D converter or digital multipliers. It produces results comparable to the correlation detector with only a slight loss (-3.5 dB) of detection sensitivity. This loss of sensitivity is more than offset by the advantages of less hardware, lower power consumption and lower costs.